1. Field of the Invention
The present invention relates generally to a semiconductor integrated circuit. More particularly, the present invention relates to a multi-threshold voltage complementary metal oxide semiconductor (MTCMOS) flip-flop, a circuit including the MTCMOS, and a method of fabricating the MTCMOS flip-flop.
A claim of priority is made to Korean Patent Application No. 10-2004-0029853 filed on Apr. 29, 2004, the disclosure of which is incorporated herein by reference in its entirety.
2. Description of the Related Art
Flip-flops are typically used as a data memory elements in digital circuits such as semiconductor integrated circuits. A flip-flop samples an input signal at a particular instant in time determined by a clock signal and converts the input signal into an output signal. Flip-flops are commonly used in semiconductor memory devices such as dynamic random access memory (DRAM) devices, processors, computers, etc.
FIG. 1 is a circuit diagram of conventional complementary metal oxide semiconductor (CMOS) hybrid-latch flip-flop disclosed in U.S. Pat. No. 6,181,180. Referring to FIG. 1, a conventional CMOS hybrid-latch flip-flop 100 includes positive channel metal oxide semiconductor (PMOS) transistors 101, 105, 106, and 107, negative channel metal oxide semiconductor (NMOS) transistors 102, 103, 104, 108, 109, and 110, a clock delay unit 120 including three inverters connected in series, and a latch unit 130 including cross-coupled inverters.
The following description relates to the operation of conventional CMOS hybrid-latch flip-flop 100. Where a clock signal CK has a logic level “low”, PMOS transistor 101 is turned on. As a result, an internal node 140 is precharged to a logic level “high”. NMOS transistors 104 and 110 are turned on whenever NMOS transistors 102 and 108 are turned off. Accordingly, an output node 150 generating an output data signal “Q” retains a previous value.
Where clock signal CK makes a transition from logic level “low” to logic level “high”, PMOS transistor 101 is turned off and NMOS transistors 102 and 108 are turned on. NMOS transistors 104 and 110 remain turned on for a delay period of clock delay unit 120. An input data signal “D” is sampled within the delay period.
Where input data signal “D” has logic level “low”, internal node 140 remains at logic level “high”. Output node 150 is then discharged to logic level “low” via NMOS transistors 108, 109, and 110, which are in a turned-on state, and remains at logic level “low” due to latch unit 130. Where input data signal “D” has logic level “high”, internal node 140 is discharged to logic level “low” via NMOS transistors 102, 103, and 104, which are in the turned-on state. Output node 150 is then charged to logic level “high” via PMOS transistor 107, which is in the turned-on state, and remains at logic level “high” due to latch unit 130.
FIG. 2 is a circuit diagram of a conventional CMOS semi-dynamic flip-flop disclosed in U.S. Pat. No. 6,181,180. Referring to FIG. 2, a conventional CMOS semi-dynamic flip-flop 200 includes PMOS transistors 201 and 205, NMOS transistors 202, 203, 204, 206, and 207, a clock delay unit 210 including two inverters connected in series, a NAND gate 220, an internal latch unit 230, and an output latch unit 240.
The following description relates to the operation of conventional CMOS semi-dynamic flip-flop 200. Where a clock signal CK is at logic level “low”, PMOS transistor 201 is turned on. As a result, an internal node 250 is precharged to logic level “high” and remains at logic level “high” due to internal latch unit 230. Meanwhile, NMOS transistor 206 is in a turned-off state. Accordingly, an output node 260 having an output data signal “Q” retains a previous value.
Where clock signal CK makes a transition from logic level “low” to logic level “high” and where an input data signal “D” is at logic level “low”, internal node 250 remains at logic level “high”. As a result, NMOS transistors 206 and 207 are turned on. Accordingly, output node 260 is discharged to logic level “low” and remains at logic level “low” due to output latch unit 240. Where input data signal “D” is at logic level “high” and clock signal CK makes a transition from logic level “low” to logic level “high”, NMOS transistors 203 and 204 are in the turned-on state and NMOS transistor 202 is in the turned-on state for a delay period of clock delay unit 210 and a delay period of NAND gate 220. As a result, internal node 250 is discharged to logic level “low”. Internal node 250 then remains low due to internal latch unit 230, and therefore, PMOS transistor 205 is turned on. Accordingly, output node 260 is charged to logic level “high” and remains high due to output latch unit 240.
To increase the integration density of semiconductor devices, a lower-power semiconductor integrated circuits are increasingly needed. A drop in power supply voltage is generally effective in implementing a low-power semiconductor integrated circuit but it usually causes transistors to be slow. To overcome this problem, a MTCMOS circuit including a metal oxide semiconductor (MOS) transistor having a low threshold voltage and a MOS transistor having a high threshold voltage is used.
A MTCMOS circuit comprises a switch circuit between a logic circuit and each of a supply voltage VDD and a ground voltage GND. The switch circuit comprises transistors having a high threshold voltage. Where the logic circuit is operating, i.e., the logic circuit is in an active mode, the switch circuit is turned on and provides supply voltage VDD or ground voltage GND to the logic circuit including the transistors having a low threshold voltage. Meanwhile, where the logic circuit is not operating, i.e., the logic circuit is in a sleep mode, the switch circuit is turned off and breaks a voltage supplied to the logic circuit. Therefore, leakage current is reduced in the logic circuit, and power consumption is minimized in an entire system. Accordingly, MTCMOS technology is very useful in reducing power consumption in portable large scale integrated (LSI) circuits having a sleep mode period much longer than an active mode period. However, where a circuit using conventional MTCMOS technology is turned off, i.e., where the circuit is in sleep mode, data stored in a flip-flop or a latch included in the logic circuit is typically lost.
Meanwhile, where flip-flops 100 and 200 shown in FIGS. 1 and 2 are used in circuits employing conventional MTCMOS technology, the following problems occur. Where flip-flops 100 and 200 include transistors having only a high threshold voltage, the circuit operates slowly. Alternatively, where flip-flops 100 and 200 include transistors having only a low threshold voltage, a large leakage current occurs in flop-flops 100 and 200. As a result, output data signal “Q” is typically not retained where the circuit is in sleep mode. Accordingly, conventional flip-flops 100 and 200 can not be applied to the circuit without modifying their design.